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VT73127/DW Datasheet(PDF) 2 Page - Vaishali Semiconductor |
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VT73127/DW Datasheet(HTML) 2 Page - Vaishali Semiconductor |
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2 / 4 page ![]() VT73127 Preliminary 2001-08-06 Page 2 MDST-0012-02 www.vaishali.com Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063 Figure 2. Pad Configuration Table 1. Pad Description Name Pad Type Description X1 1 Xi Crystal connection. Connect to a 27 MHz pullable crystal VDD1 2 P Core VDD. Connect to 3.3V VIN 3 I Tuning control input. Zero to 3.3V signal controls the frequency of the VCXO. GND 4 P Connect to ground. CLK 5 O Clock output OE 6 I Active HIGH output enable. When LOW, the output is held in a tri-state condition VDD2 7 P Output buffer VDD . Connect to 3.3V GND 8 P Connect to ground. X2 9 Xi Crystal connection. Connect to a 27 MHz pullable crystal. Legend: I = Input O = Output P = Power supply connection Xi = Crystal connections. Table 2. Absolute Maximum Ratings Parameter Conditions Min Typ Max Units Supply voltage, VDD Referenced to GND 7 V Inputs and Clock Outputs Referenced to GND -0.5 VDD+0.5 V Soldering Temperature Max of 10 seconds 260 °C Storage temperature -65 150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3. Operating Conditions Parameter Conditions Min Typ Max Units Operating Voltage, VDD 3.0 3.3 3.6 V Input High Voltage, VIH, X1 pin only 2.5 V Input Low Voltage, VIL, X1 pin only 0.4 V Operating Temperature 0 70 °C Input crystal accuracy ±30 ppm GND VIN VDD1 X1 X2 VDD2 GND VT73127/D OE CLK 1 2 3 4 5 7 8 9 6 |
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