LPC2157_09 datasheet(13/45 Pages) NXP

13 / 45 page

LPC2157_2158_2

Product data sheet

Rev. 02 — 9 February 2009

13 of 45

NXP Semiconductors

LPC2157/2158

Single-chip 16-bit/32-bit microcontrollers

P0[31]/UP_LED/

CONNECT

5[6]

P0[31] — General purpose output only digital pin.

UP_LED — USB GoodLink LED indicator. It is LOW when device is conﬁgured

(non-control endpoints enabled). It is HIGH when the device is not conﬁgured

or during global suspend.

CONNECT — Signal used to switch an external 1.5 k

Ω resistor under the

software control. Used with the SoftConnect USB feature.

Important: This is an digital output only pin. This pin MUST NOT be externally

pulled LOW when RESET pin is LOW or the JTAG port will be disabled.

P1[0] to P1[31]

I/O

Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 1 pins depends upon the pin function

selected via the pin connect block. Pins 0 through 15 and 18 through 24 of

port 1 are not available.

P1[16]

4[6]

I/O

P1[16] — General purpose input/output digital pin (GPIO).

P1[17]

100[6]

I/O

P1[17] — General purpose input/output digital pin (GPIO).

P1[25]/EXTIN0

16[6]

I/O

P1[25] — General purpose input/output digital pin (GPIO).

EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

P1[26]/RTCK

12[6]

I/O

P1[26] — General purpose input/output digital pin (GPIO).

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bidirectional pin with internal pull-up.

Note: LOW on RTCK while RESET is LOW enables pins P1[31:26] to operate

as Debug port after reset.

P1[27]/TDO

90[6]

I/O

P1[27] — General purpose input/output digital pin (GPIO).

TDO — Test Data out for JTAG interface.

P1[28]/TDI

86[6]

I/O

P1[28] — General purpose input/output digital pin (GPIO).

TDI — Test Data in for JTAG interface.

P1[29]/TCK

82[6]

I/O

P1[29] — General purpose input/output digital pin (GPIO).

TCK — Test Clock for JTAG interface. This clock must be slower than 1

⁄6 of the

CPU clock (CCLK) for the JTAG interface to operate.

P1[30]/TMS

78[6]

I/O

P1[30] — General purpose input/output digital pin (GPIO).

TMS — Test Mode Select for JTAG interface.

P1[31]/TRST

8[6]

I/O

P1[31] — General purpose input/output digital pin (GPIO).

TRST — Test Reset for JTAG interface.

D+

98[7]

I/O

USB bidirectional D+ line.

−

99[7]

I/O

USB bidirectional D

− line.

RESET

83[8]

External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

88[9]

Input from the oscillator ampliﬁer.

XTAL2

87[9]

Output to the oscillator circuit and internal clock generator circuits.

RTCX1

93[9]

Input to the RTC oscillator circuit.

RTCX2

94[9]

Output from the RTC oscillator circuit.

VSS

6, 13, 32,

39, 40,

85, 95

Ground: 0 V reference.

Table 3.

Pin description LPC2158 …continued

Symbol

Type

Description

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