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ADT7484AARMZ-R7 Datasheet(PDF) 4 Page - ON Semiconductor |
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ADT7484AARMZ-R7 Datasheet(HTML) 4 Page - ON Semiconductor |
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4 / 14 page ![]() ADT7484A/ADT7486A http://onsemi.com 4 ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, = VCC = VMIN to VMAX, unless otherwise noted) Parameter Unit Max Typ Min Conditions Temperature-to-Digital Converter Conversion Time (Local Temperature) (Note 1) Averaging enabled 12 12 ms Conversion Time (Remote Temperature) (Note 1) Averaging enabled 38 ms Total Monitoring Cycle Time (Note 1) Averaging enabled 50 ms Digital Inputs (ADD0, ADD1) Input High Voltage, VIH 2.3 V Input Low Voltage, VIL 0.8 V Input High Current, IIH VIN = VCC −1.0 mA Input Low Current, IIL VIN = 0 1.0 mA Pin Capacitance 5.0 pF Digital I/O (SST Pin) Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.4 V Hysteresis (Note 1) Between input switching levels 150 mV Output High Voltage, VOH ISOURCE = 6 mA (maximum) 1.1 1.9 V High Impedance State Leakage, ILEAK Device powered on SST bus; VSST = 1.1 V, VCC = 3.3 V ±1.0 mA High Impedance State Leakage, ILEAK Device unpowered on SST bus; VSST = 1.1 V, VCC = 0 V ±10 mA Signal Noise Immunity, VNOISE Noise glitches from 10 MHz to 100 MHz; width up to 50 ns 300 mV p-p SST Timing Bitwise Period, tBIT 0.495 500 ms High Level Time for Logic 1, tH1 (Note 2) tBIT defined in speed negotiation 0.6 x tBIT 0.75 x tBIT 0.8 x tBIT ms High Level Time for Logic 0, tH0 (Note 2) 0.2 x tBIT 0.25 x tBIT 0.4 x tBIT ms Time to Assert SST High for Logic 1, tSU, HIGH 0.2 x tBIT ms Hold Time, tHOLD (Note 3) See SST Specification Rev 1.0 0.5 x tBIT−M ms Stop Time, tSTOP Device responding to a constant low level driven by originator 1.25 x tBIT 2 x tBIT 2 x tBIT ms Time to Respond After a Reset, tRESET 0.4 ms Response Time to Speed Negotiation After Powerup Time after powerup when device can participate in speed negotiation 500 ms 1. Guaranteed by design, not production tested. 2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse. 3. Devices compatible with hold time specification as driven by SST originator. |
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