UR5596L-S08-R datasheet(6/12 Pages) UTC

6 / 12 page

UR5596

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

6 of 12

www.unisonic.com.tw

QW-R502-045,C

CAPACITOR SELECTION

A capacitor is recommended for improve performance during large load transients to prevent the input rail from

dropping, even though UR5596 does not require for input stability. The input capacitor should be located as close as

possible to the PVIN pin. The typical recommended value for AL electrolytic capacitors is 50 µF and 10 µF with X5R

or better for Ceramic capacitors. If AVIN and PVIN are separated, the 47µF capacitor should be placed as close to

possible to the PVIN rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive

noise from coupling into the device.

UTC UR5596 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance).

The choice for output capacitor depends on the application and the requirements for load transient response of VTT.

As a general recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL

applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected

and the extent at which the output voltage is allowed to droop.

THERMAL DISSIPATION

The UR5596 will generate heat result from internal power dissipation when current flow working. The device might

be damaged any beyond maximum junction temperature rating. The maximum allowable internal temperature rise

(TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum

allowable junction temperature (TJmax).

TRmax = TJmax − TAmax

From this equation, the maximum power dissipation (PDmax) of the part can be calculated:

PDmax = TRmax / θJA

The θJA of UR5596 can be calculated (refer to JEDEC standard) and will depend on several package type,

materials, ambient air temperature and so on.

UR5596L-S08-R Datasheet(PDF) 6 Page - Unisonic Technologies