L9950XPTR datasheet(15/39 Pages) STMICROELECTRONICS

15 / 39 page

L9950 - L9950XP

Electrical specifications

Doc ID 10311 Rev 10

15/39

Note:

DI timing parameters tested in production by a passed/failed test:

Tj=-40 °C/+25 °C: SPI communication @2 MHZ.

Tj=+125 °C: SPI communication @1.25 MHZ.

Table 14.

DI timing

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tCLK

Clock period

VCC = 5 V

1000

tCLKH

Clock high time

VCC = 5 V

400

tCLKL

Clock low time

VCC = 5 V

400

tset CSN

CSN setup time, CSN low

before rising edge of CLK

VCC = 5 V

400

tset CLK

CLK setup time, CLK high

before rising edge of CSN

VCC = 5 V

400

tset DI

DI setup time

VCC = 5 V

200

thold time DI hold time

VCC = 5 V

200

tr in

Rise time of input signal DI,

CLK, CSN

VCC = 5 V

100

tf in

Fall time of input signal DI,

CLK, CSN

VCC = 5 V

100

Table 15.

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDOL

Output low level

VCC = 5 V, ID = -2 mA

0.2

0.4

VDOH

Output high level

VCC = 5 V, ID = 2 mA

VCC -0.4 VCC-0.2

IDOLK

Tristate leakage current

VCSN = VCC,

0V < VDO < VCC

-10

µA

CDO

(1)

Value of input capacity is not measured in production test. Parameter guaranteed by design.

Tristate input

capacitance

VCSN = VCC,

0V < VCC < 5.3 V

-10

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