SPC56EL60L5 datasheet(18/160 Pages) STMICROELECTRONICS

18 / 160 page

Introduction

SPC56XL60/54

18/160

Doc ID 15457 Rev 8

1.5.13

System clocks and clock generation

The following list summarizes the system clock and clock generation on this device:

●

Lock status continuously monitored by lock detect circuitry

●

Loss-of-clock (LOC) detection for reference and feedback clocks

●

On-chip loop filter (for improved electromagnetic interference performance and fewer

external components required)

●

Programmable output clock divider of system clock (

÷1, ÷2, ÷4, ÷8)

●

FlexPWM module and as many as three eTimer modules running on an auxiliary clock

independent from system clock (with max frequency 120 MHz)

●

On-chip crystal oscillator with automatic level control

●

Dedicated internal 16 MHz internal RC oscillator for rapid start-up

–

Supports automated frequency trimming by hardware during device startup and by

user application

●

Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and

SWG)

1.5.14

Frequency-Modulated Phase-Locked Loop (FMPLL)

Each device has two FMPLLs.

Each FMPLL allows the user to generate high speed system clocks starting from a minimum

reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency

modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio

are all software configurable. The FMPLLs have the following major features:

●

Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)

●

Voltage controlled oscillator (VCO) range: 256–512 MHz

●

Frequency modulation via software control to reduce and control emission peaks

–

Modulation depth ±2% if centered or 0% to –4% if downshifted via software control

–

Modulation frequency: triangular modulation with 25 kHz nominal rate

●

Option to switch modulation on and off via software interface

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Output divider (ODF) for reduced frequency operation without re-lock

●

3 modes of operation

–

Bypass mode

–

Normal FMPLL mode with crystal reference (default)

–

Normal FMPLL mode with external reference

●

Lock monitor circuitry with lock status

●

Loss-of-lock detection for reference and feedback clocks

●

Self-clocked mode (SCM) operation

●

On-chip loop filter

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