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Data Sheet

AD8422

Rev. 0 | Page 19 of 24

THEORY OF OPERATION

+IN

–IN

+VS

–VS

10kΩ

+VS

–VS

OUTPUT

REF

NODE 1

NODE 2

COMPENSATION

+VS

10kΩ

9.9kΩ

DIFFERENCE

AMPLIFIER STAGE

ESD AND

OVERVOLTAGE

PROTECTION

ESD AND

OVERVOLTAGE

PROTECTION

superβ

NODE 3

NODE 4

superβ

–VS

Figure 57. Simplified Schematic

ARCHITECTURE

The AD8422 is based on the classic 3-op-amp instrumentation

amplifier topology. This topology has two stages: a preamplifier

to provide differential amplification followed by a difference

amplifier that removes the common-mode voltage. Figure 57

shows a simplified schematic of the AD8422.

Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as

precision current feedback amplifiers that maintain a fixed

current in the emitters of Q1 and Q2. Any change in the input

signal forces the output voltages of A1 and A2 to change accord-

ingly and maintain the Q1 and Q2 current at the correct value.

This causes a precise diode drop from –IN and +IN to Node 3

and Node 4, respectively, so that the differential signal applied

to the inputs is replicated across the RG pins. Any current

through RG must also flow through R1 and R2, creating the

gained differential voltage between Node 1 and Node 2.

The amplified differential signal and the common-mode signal

are applied to a difference amplifier that rejects the common-

mode voltage but preserves the amplified differential voltage.

Laser-trimmed resistors allow for a highly accurate in-amp with a

gain error of less than 0.01% and a CMRR that exceeds 94 dB

(G = 1). The supply current is precisely trimmed to reduce

uncertainties due to part-to-part variations in power dissipation

and noise. The high performance pinout and special attention to

design and layout allow for high CMRR across a wide frequency

and temperature range. Using superbeta input transistors and

bias current compensation, the AD8422 offers extremely high

input impedance and low bias current, as well as very low voltage

noise while using only 300 µA supply current. The overvoltage

protection scheme allows the input to go 40 V from the opposite

rail at all gains without compromising the noise performance.

The transfer function of the AD8422 is

VOUT = G × (VIN+ − VIN−) + VREF

where:

kΩ

19.8

GAIN SELECTION

Placing a resistor across the RG terminals sets the gain of the

AD8422 that can be calculated by referring to Table 6 or by

using the following gain equation:

kΩ

19.8

−

The AD8422 defaults to G = 1 when no gain resistor is used. Add

the tolerance and gain drift of the RG resistor to the specifications

of the AD8422 to determine the total gain accuracy of the system.

When the gain resistor is not used, gain error and gain drift are

minimal.

Table 6. Gains Achieved Using 1% Resistors

1% Standard Table Value of RG (Ω)

Calculated Gain

19.6 k

2.010

4.99 k

4.968

2.21 k

9.959

1.05 k

19.86

402

50.25

200

100.0

100

199.0

39.2

506.1

991.0

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