STM32F101XC_11 datasheet(74/112 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F101xC, STM32F101xD, STM32F101xE

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Doc ID 14610 Rev 8

NAND controller waveforms and timings

Figure 35 through Figure 38 represent synchronous waveforms and Table 40 provides the

corresponding timings. The results shown in this table are obtained with the following FSMC

configuration:

●

COM.FSMC_SetupTime = 0x01;

●

COM.FSMC_WaitSetupTime = 0x03;

●

COM.FSMC_HoldSetupTime = 0x02;

●

COM.FSMC_HiZSetupTime = 0x01;

●

ATT.FSMC_SetupTime = 0x01;

●

ATT.FSMC_WaitSetupTime = 0x03;

●

ATT.FSMC_HoldSetupTime = 0x02;

●

ATT.FSMC_HiZSetupTime = 0x01;

●

Bank = FSMC_Bank_NAND;

●

MemoryDataWidth = FSMC_MemoryDataWidth_16b;

●

ECC = FSMC_ECC_Enable;

●

ECCPageSize = FSMC_ECCPageSize_512Bytes;

●

TCLRSetupTime = 0;

●

TARSetupTime = 0;

td(D-NWE)

FSMC_D[15:0] valid before FSMC_NWE high

13tHCLK

tw(NIOWR)

FSMC_NIOWR low width

8tHCLK + 3

tv(NIOWR-D)

FSMC_NIOWR low to FSMC_D[15:0] valid

5tHCLK +1

th(NIOWR-D)

FSMC_NIOWR high to FSMC_D[15:0] invalid

11tHCLK

td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid

5tHCLK+3ns

th(NCEx-NIOWR)

th(NCE4_1-NIOWR)

FSMC_NCEx high to FSMC_NIOWR invalid

FSMC_NCE4_1 high to FSMC_NIOWR invalid

5tHCLK – 5

td(NIORD-NCEx)

td(NIORD-NCE4_1)

FSMC_NCEx low to FSMC_NIORD valid

FSMC_NCE4_1 low to FSMC_NIORD valid

5tHCLK + 2.5

th(NCEx-NIORD)

th(NCE4_1-NIORD)

FSMC_NCEx high to FSMC_NIORD invalid

FSMC_NCE4_1 high to FSMC_NIORD invalid

5tHCLK – 5

tsu(D-NIORD)

FSMC_D[15:0] valid before FSMC_NIORD high

4.5

td(NIORD-D)

FSMC_D[15:0] valid after FSMC_NIORD high

tw(NIORD)

FSMC_NIORD low width

8tHCLK + 2

CL = 15 pF.

Based on characterization, not tested in production.

Table 39.

Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued)

Symbol

Parameter

Min

Max

Unit

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