Product Specification

PE83336

Page 3 of 12

Document No. 70-0137-05 │ www.psemi.com

©2010-2012 Peregrine Semiconductor Corp. All rights reserved.

Table 1. Pin Descriptions (continued)

Pin No.

(44-lead

CQFJ)

Pin

Name

Interface

Mode

Type

Description

14

Sdata

Serial

Input

Binary serial data input. Input data entered MSB first.

Parallel

Input

Parallel data bus bit5.

Direct

Input

M Counter bit5.

15

Sclk

Serial

Input

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the

8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.

Parallel

Input

Parallel data bus bit6.

Direct

Input

M Counter bit6.

16

FSELS

Serial

Input

Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for

programming of internal counters while in Serial Interface Mode.

Parallel

Input

Parallel data bus bit7 (MSB).

Pre_en

Direct

Input

17

GND

ALL

Ground.

18

FSELP

Parallel

Input

Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for

programming of internal counters while in Parallel Interface Mode.

Direct

Input

A Counter bit0 (LSB).

19

E_WR

Serial

Input

Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into

the enhancement register on the rising edge of Sclk.

Parallel

Input

Enhancement register write. D[7:0] are latched into the enhancement register on the rising

edge of E_WR.

Direct

Input

A Counter bit1.

20

M2_WR

Parallel

Input

M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of

M2_WR.

Direct

Input

A Counter bit2.

21

Smode

Serial,

Parallel

Input

Selects serial bus interface mode (

Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0,

Smode=0).

Direct

Input

A Counter bit3 (MSB).

22

Bmode

ALL

Input

Selects direct interface mode (

Bmode=1).

23

ALL

(Note 1)

Same as pin 1.

24

M1_WR

Parallel

Input

M1 write. D[7:0] are latched into the primary register (

Pre_en, M[6:0]) on the rising edge of

M1_WR.

25

A_WR

Parallel

Input

A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of

A_WR.

26

Hop_WR

Serial,

Parallel

Input

Hop write. The contents of the primary register are latched into the secondary register on the

rising edge of Hop_WR.

27

ALL

Input

Prescaler input from the VCO. 3.0 GHz max frequency.

28

ALL

Input

Prescaler complementary input. A bypass capacitor should be placed as close as possible to

this pin and be connected in series with a 50

Ω resistor directly to the ground plane.

29

GND

ALL

Ground.