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PIC10F320T-EMCSQTP Datasheet(PDF) 83 Page - Microchip Technology

Part # PIC10F320T-EMCSQTP
Description  6/8-Pin, High-Performance, Flash Microcontrollers
PDF  210 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC10F320T-EMCSQTP Datasheet(HTML) 83 Page - Microchip Technology

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 2011 Microchip Technology Inc.
Preliminary
DS41585A-page 83
PIC10(L)F320/322
11.6
Interrupt-On-Change Registers
REGISTER 11-1:
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented
: Read as ‘0’.
bit 3-0
IOCAP<3:0>:
Interrupt-on-change PORTA Positive Edge Enable bits
1
= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.(1)
0
= Interrupt-on-Change disabled for the associated pin.
Note 1:
Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).
REGISTER 11-2:
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented
: Read as ‘0’.
bit 3-0
IOCAN<3:0>:
Interrupt-on-change PORTA Negative Edge Enable bits
1
= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.(1)
0
= Interrupt-on-Change disabled for the associated pin.
Note 1:
Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).



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