DS1642 datasheet(4/11 Pages) DALLAS

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DS1642

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RETRIEVING DATA FROM RAM OR CLOCK

The DS1642 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The

device architecture allows ripple–through access to any of the address locations in the NV SRAM. Valid

data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE

and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be

available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the

data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data

lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE

remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1642 is in the write mode whenever WE and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout

the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or

write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a

typical application, the OE signal will be high during a write cycle. However, OE can be active provided

that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low

the data bus can become active with read data defined by the address inputs. A low transition on WE will

then disable the outputs tWEZ after WE goes active.

DATA RETENTION MODE

When VCC is within nominal limits (VCC > 4.5 volts) the DS1642 can be accessed as described above by

read or write cycles. However, when VCC is below the power-fail point VPF (point at which write

protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished

internally by inhibiting access via the CE signal. When VCC falls below the level of the internal battery

supply, power input is switched from the VCC pin to the internal battery and clock activity, RAM, and

clock data are maintained from the battery until VCC is returned to nominal level.

BATTERY LONGEVITY

The DS1642 has a lithium power source that is designed to provide energy for clock activity, and clock

and RAM data retention when the VCC supply is not present. The capability of this internal power supply

is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For

specification purposes, the life expectancy is 10 years at 25

°C with the internal clock oscillator running in

the absence of VCC power. Each DS1642 is shipped from Dallas Semiconductor with its lithium energy

source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than

VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the

DS1642 will be much longer than 10 years since no lithium battery energy is consumed when VCC is

present.

DS1642 Datasheet(PDF) 4 Page - Dallas Semiconductor