ST1005SRG

P Channel Enhancement Mode MOSFET

-0.8A

STANSON TECHNOLOGY

120 Bentley Square, Mountain View, Ca 94040 USA

www.stansontech.com

ST1005SRG 2013. Rev.1

DESCRIPTION

ST1005SRG is the P-Channel logic enhancement mode power field effect transistor

which is produced using high cell density, DMOS trench technology. This high density

process is especially tailored to minimize on-state resistance. These devices are

particularly suited for low voltage application such as cellular phone and notebook

computer power management, other battery powered circuits, and low in-line power

loss are required. The product is in a very small outline surface mount package.

PIN CONFIGURATION

SOT-23

1.Gate

2.Source

3.Drain

PART MARKING

SOT-23

Y: Year Code

A: Process Code

FEATURE

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@VGS = -10V

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@VGS = -4.5V

l

Super high density cell design for

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Exceptional on-resistance and maximum

DC current capability

l

SOT-23 package design

3

1

2

D

G

S

3

1

2

105YA