6

FIGURE 4. MODE 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES

FIGURE 5. INPUT PORT MODE 0 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION

HIGH

IMPEDANCE

DATA BUS

SR

CLEAR

DATA IN

CLOCK

CS1 - CS2

(NOTE 1)

MODE 0 TRUTH TABLE

CLOCK

† CS1-CS2

CLEAR

DATA OUT EQUALS

X

0

X

High Impedance

010

0

011

Data Latch

1

1

X

Data In

† CS1

SERVICE REQUEST TRUTH TABLE

CLOCK

CS1 or CS2

or CLEAR

SR/SR

0

SR/SR

1

NOTE 1. CS1

• CS2 is the overlap of CS1 = 1 and CS2 = 1.

CS2

CDP1852

DATA BUS

CS1

SR

MODE

D0

D1

CLOCK

STROBE

DATA FROM

PERIPHERAL

CDP1802

MRD

MEMORY

ADDRESS

LINES

PERIPHERAL DEVICE

PLACES DATA IN CDP1852

AND CDP1852 SIGNALS

CDP1802 THAT DATA IS READY

VALID

THREE - STATE

DATA BUS

MRD

SR/SR

PERIPHERAL

STROBE

DATA

CDP1802 SELECTS

CDP1852 AND DATA

IS TRANSFERRED

TO MEMORY AND

THE MICROPROCESSOR

CDP1852, CDP1852C