© 1996 Microchip Technology Inc.

Preliminary

DS21163B-page 3

24C32A

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Vcc = 4.5-5.5

Units

Remarks

Min

Max

Clock frequency

—

100

kHz

Clock high time

4000

—

ns

Clock low time

4700

—

ns

SDA and SCL rise time

—

1000

ns

(Note 1)

SDA and SCL fall time

—

300

ns

(Note 1)

START condition hold time

4000

—

ns

After this period the first clock

pulse is generated

START condition setup time

4700

—

ns

Only relevant for repeated

START condition

Data input hold time

0—

ns

Data input setup time

250

—

ns

STOP condition setup time

4000

—

ns

Output valid from clock

—

3500

ns

(Note 2)

Bus free time

4700

—

ns

Time the bus must be free before

a new transmission can start

—

250

ns

≤ 100 pF

Input filter spike suppression

(SDA and SCL pins)

—

50

ns

(Note 3)

Write cycle time

—5

ms

Endurance

—

1M

—

cycles

25

°C, Vcc = 5.0V, Block Mode

(Note 4)

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

SCL

SDA

IN

SDA

OUT