SM5843A

×1

NIPPON PRECISION CIRCUITS—17

Audio Data Input (INF1N, INF2N, IW1N,

IW2N, DI, DIL, DIR, BCKI, LRCI)

The input data format and several input pin functions

are selected by the state of INF1N and INF2N.

The input data word length is selected by the state of

IW1N and IW2N when INF1N is LOW. 20-bit is

selected when INF1N is HIGH.

Jitter-free Function (SYNCN)

The arithmetic circuit and output control timing is

derived from the system clock, and is therefore inde-

pendent of the input LRCI and BCKI clocks.

Accordingly, any jitter in the data input clock (LRCI

and BCKI) does not cause jitter in the output.

Generally, the internal timing is synchronized to the

LRCI input timing after a system reset release, when

RSTN goes from LOW to HIGH, on the first LRCI

clock start edge. If the input timing and LRCI start

edge timing subsequently drift, the input timing is

automatically resynchronized when the timing error

exceeds a certain value. There are 2 timing error val-

ues at which resynchronization occurs, selected by

the state of SYNCN.

Jitter-free mode (SYNCN = HIGH)

When SYNCN is HIGH, the timing error value is

±3/8

× (LRCI clock period). When the difference

between the input timing and LRCI start edge posi-

tion do not exceed this value, internal timing is not

resynchronized and all functions continue to operate

normally.

Sync mode (SYNCN = LOW)

When SYNCN is LOW, the timing error value is ±1

× (system clock period), which is a much smaller

timing error tolerance than in jitter-free mode. In this

mode, the internal timing is guaranteed to follow the

LRCI clock timing within this tolerance, making this

mode useful for systems constructed from a multiple

number of SM5843A

×1 devices.

Note that resynchronization affects the internal oper-

ation and can generate a momentary click noise out-

put.

Audio Data Output (DOL, DOR, BCKO, WCKO, OW20N)

The output data is in serial, simultaneous left and

right-channel, 2s complement, MSB first, BCKO

burst (NPC format) format. The output data word

length is selected by the state of OW20N. 18-bit out-

put is selected when OW20N is HIGH, and 20-bit

output when OW20N is LOW.

8fs serial data is output in sync with the falling edge

of the internal system clock and BCKO clock. The

number of BCKO bit clock pulses per word changes

depending on the output bit length selected (18/20

bits). Consequently, output data is latched into the

internal output register on the falling of the edge of

an output word clock WCKO, which has timing

independent of the number of output bits as specified

in the following table.

INF1N

DI/INF2N

Input format

Pin function selection

DI/INF2N

IW1N/DIL

IW2N/DIR

LOW

LOW

DI

IW1N

IW2N

LOW

HIGH

HIGH

LOW

LR alternating, leading data

INF2N

DIL

DIR

HIGH

HIGH

1. Alternating left-channel and right-channel data input on a single input DI.

2. Simultaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively.

INF1N

IW2N/DIL

IW1N/DIR

Input bit length

LOW

LOW

LOW

20 bits

LOW

HIGH

20 bits

HIGH

LOW

18 bits

HIGH

HIGH

16 bits

HIGH

××

20 bits

Parameter

Symbol

CKSLN = HIGH

CKSLN = LOW

Bit clock rate

1/192fs

1/256fs

Data word length