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4

Recommended Operating Conditions

Absolute Maximum Ratings*

+5V ± 5%

differential voltage between any two GND’s

<10mV

analog input voltage range (full scale)

1.25 – 3.25V

digital input voltage range

operating temperature range

0°C to 70°C

> 25ns

-0.5V to +7V

differential voltage between any two GND’s

200mV

analog input voltage range

digital input voltage range

output short circuit duration (one pin to gnd)

infinite

junction temperature

+175°C

storage temperature range

-65°C to +150°C

lead solder duration (+300°C)

10 sec

*NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired.

Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device

reliability.

Pinout & Pin Description and Usage

internal reference points which should be bypassed to

GND with a 0.1

µF capacitor.

voltage that is equal to the mid point of the reference

range and can be used to apply the appropriate offset to

the analog inputs. For a more detailed discussion on

references, see the paragraph on references in the

applications section of this datasheet.

The analog input to the CLC949 is a differential signal

inputs, see the paragraphs in the applications section of

this datasheet.

The power and ground pins of the CLC949 are split into

those that supply the analog portions of the integrated

ground planes, then performance can be improved by

making use of the appropriate pins. In many systems,

the power pins will all be tied together and the GND pins

will all be tied together. For more detailed discussion,

please refer to the paragraph on power and grounds in

the applications section of the databook.

Clock (CLK)

The CLK accepts a CMOS clock input.

Samples are

taken on the falling edges of the CLK and data emerges

6 1/2 clock cycles later, on to the rising edge of the CLK.

Output Data (D1-D12, MSBINV, OE\)

The data emerges from the CLC949 as CMOS level

digital data on D1(MSB) through D12(LSB). The

outputs can be put into a high impedance state by

bringing OE\ high.

There is an internal pulldown

resistor so that if this input is left open, the output data is

enabled. MSBINV will invert the MSB of the output data.

With MSBINV in the high state, the output data is two’s

complement, when low, the output data format is offset

binary. An internal pulldown resistor makes the output

default to offset binary if MSBINV is left open.

Bias Control (BCO, BC1, BIASC)

The DC bias current of the CLC949 is controlled by three

pins: BCO, BC1, and BIASC. BC0 and BC1 are digital

CMOS inputs and set the bias current in accordance with

the truth table below:

BC0

BC1

Bias Current

PD@10MSPS

0

0

Default: Med Bias (200

µA)

200mW

1

0

Analog Mode

Variable

0

1

High Bias (400

µA)

350mW

1

1

Low Bias (50

µA)

75mW

In the analog mode, the user provides a bias current

through the BIASC pin of the CLC949.

As the bias

current is increased, the power dissipation of the CLC949

is increased and the part becomes capable of increased

conversion rates.

NC

No connection - leave these pins open.

44-Pin PLCC

TOP VIEW

1

2

3

4

5

6

44 43 42 41 40

23

22

21

20

19

18

24 25 26 27 28

12

11

10

9

8

7

13

14

15

16

17

NC

BIASC

34

35

36

37

38

39

33

32

31

30

29

D8

D7

D6

D5

D4

D3

D9

D10

D11

D12(LSB)

BCO