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AS7C256 Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation

Part # AS7C256
Description  High Performance 32Kx8 CMOS SRAM
PDF  8 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C256 Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation

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AS7C256
AS7C256L
4
Parameter
Symbol
-10
-12
-15
-20
-25
-35
Unit
Notes
Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
tRC
10
–
12
–
15
–
20
–
25
–
35
–
ns
Address Access Time
tAA
–
10
–
12
–
15
–
20
–
25
–
35
ns
3
Chip Enable (CE) Access Time
tACE
–
10
–
12
–
15
–
20
–
25
–
35
ns
3
Output Enable (OE) Access Time
tOE
–3
–3
–4–
5–
6–
8
ns
Output Hold from Address Change
tOH
2–
3–
3–3
–3
–3
–
ns
5
CE LOW to Output in Low Z
tCLZ
3–
3–
3–3
–3
–3
–
ns
4, 5
CE HIGH to Output in High Z
tCHZ
–3
–3
–4–
5–
6–
8
ns
4, 5
OE LOW to Output in Low Z
tOLZ
0–
0–
0–0
–0
–0
–
ns
4, 5
OE HIGH to Output in High Z
tOHZ
–3
–3
–4–
5–
6–
8
ns
4, 5
Power Up Time
tPU
0–
0–
0–0
–0
–0
–
ns
4, 5
Power Down Time
tPD
–
10
–
12
–
15
–
20
–
25
–
35
ns
4, 5
READ CYCLE
(VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)
3, 9
3, 6, 7, 9
TIMING WAVEFORM OF READ CYCLE 1
(Address Controlled)
Address
Dout
Data Valid
tOH
tAA
tRC
3, 6, 8, 9
TIMING WAVEFORM OF READ CYCLE 2
(CE Controlled)
Supply
Current
CE
OE
Dout
tRC
1
tOE
tOLZ
tACE
tCHZ
tCLZ
tPU
tPD
ICC
ISB
50%
50%
tOHZ
Data Valid
AS7C256-04



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