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PCM5252 Datasheet(PDF) 13 Page - Texas Instruments |
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PCM5252 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 119 page ![]() XSMT 0.9 * DV DD t r t f <20ns <20ns 0.1 * DV DD BCK tBCH tBCL tBCY tDS tDH tLRD DATA LRCK 0. 5 * DVDD 0. 5 * DVDD 0. 5 * DVDD ( Output) ( Output) ( Output) tDOD DATA 0. 5 * DVDD ( Input) PCM5252 www.ti.com SLASE63 – NOVEMBER 2014 The I2S master timing is shown in Figure 6. MIN TYP MAX UNIT tBCY BCK Pulse Cycle Time 40 ns tBCL BCK Pulse Width LOW 16 ns tBCH BCK Pulse Width HIGH 16 ns tBCK BCK frequency at DVDD = 3.3V 24.576 MHz tBCK(1.8V) BCK frequency at DVDD = 1.8V 12.288 MHz tLRD LRCKx delay time from BCKx falling edge –10 20 ns tDS DATA Set Up Time 8 ns tDH DATA Hold Time 8 ns tDOD DATA delay time from BCK falling edge at DVDD = 3.3V 15 ns tDOD(1.8V) DATA delay time from BCK falling edge at DVDD = 1.8V 20 ns Figure 6. PCM5252 Serial Audio Timing - Master 8.9 Timing Requirements: XSMT MIN TYP MAX UNIT tr Rise time 20 ns tf Fall time 20 ns Figure 7. XSMT Timing for Soft Mute and Soft Un-Mute Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: PCM5252 |
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