| Electronic Components Datasheet Search |
|
AS5C1008 Datasheet(PDF) 3 Page - Micross Components |
|
|
|||||||||||||||||||||||||||||
AS5C1008 Datasheet(HTML) 3 Page - Micross Components |
|
3 / 10 page ![]() SRAM AS5C1008 AS5C1008 Rev. 3.9 10/10 Micross Components reserves the right to change products or specifications without notice. 3 PARAMETER CONDITIONS SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS Dynamic Operating Current Vcc=MAX, IOUT = 0mA, CE1 = VIL and CE2 = VIH, f = fmax ICC1 180 150 140 125 mA TTL Standby Current - TTL Inputs Vcc=MAX, VIN = VIH or VIL, CE\1> VIH and CE2 > VIL, f = fmax ISB1 90 75 70 60 mA CMOS Standby Current - CMOS Inputs Vcc=MAX, CE\1 > Vcc -0.2V, or CE2 < 0.2V, VIN > Vcc -0.2V and VIN < 0.2V, f = 0 ISB2 10 10 10 10 mA Input Leakage Current GND < VIN < Vcc ILI -10 10 -10 10 -10 10 -10 10 A Output Leakage Current GND < VOUT < Vcc Output Disabled ILO -10 10 -10 10 -10 10 -10 10 A Output High Voltage Vcc = MIN, IOH = -4.0 mA VOH 2.42.4 2.42.4 V Output Low Voltage Vcc = MIN, IOL = 8.0 mA VOL 0.4 0.4 0.4 0.4 V Input High Voltage VIH 2.2 Vcc +0.5 2.2 Vcc +0.5 2.2 Vcc +0.5 2.2 Vcc +0.5 V Input Low Voltage VIL -0.5 0.8 -0.5 0.8 -0.5 0.8 -0.5 0.8 V -15 -20 -25 -35 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC<T A <+125oC or -40oC to +85oC; Vcc = 5V+10%) PIN DESCRIPTIONS A0 - A16: Address Inputs These 17 address inputs select one of the 131,072 8-bit words in the RAM. CE\ 1 : Chip Enable 1 Input CE\ 1 is asserted LOW to read from or write to the device. If Chip Enable 1 is deasserted, the device is deselected and is in standby power mode. The I/O pins will be in the high- impedance state when the device is deselected. CE 2 : Chip Enable 2 Input CE 2 is asserted HIGH to read from or write to the device. If Chip Enable 2 is deasserted, the device is deselected and is in standby power mode. The I/O pins will be in the high- impedance state when the device is deselected. OE\: Output Enable Input The Output Enable Input is asserted LOW. If asserted LOW while CE\ 1 is asserted (LOW) and CE 2 is asserted (HIGH) and WE\ is deasserted (HIGH), data from the SRAM will be present on the I/O pins. The I/O pins will be in the high-impedance state when OE\ is deasserted. WE\: Write Enable Input The Write Enable input is asserted LOW and controls read and write operations. When CE\ 1 and WE\ are both asserted (LOW) and CE 2 is asserted (HIGH) input data present on the I/O pins will be written into the selected memory location. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |