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STS8DNH3LL Datasheet(PDF) 1 Page - STMicroelectronics |
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STS8DNH3LL Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 9 page ![]() 1/9 June 2004 STS8DNH3LL DUAL N-CHANNEL 30V - 0.018 Ω - 8A SO-8 LOW GATE CHARGE STripFET™ III POWER MOSFET Rev.0.2 ■ TYPICAL RDS(on) = 0.018 Ω ■ OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V ■ CONDUCTION LOSSES REDUCED ■ SWITCHING LOSSES REDUCED DESCRIPTION This application specific MOSFET is the Third generation of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCS Ordering Information TYPE VDSS RDS(on) ID STS8DNH3LL 30 V <0.022 Ω 8 A SALES TYPE MARKING PACKAGE PACKAGING STS8DNH3LL S8DNH3LL SO-8 TAPE & REEL SO-8 ABSOLUTE MAXIMUM RATINGS ( •) Pulse width limited by safe operating area. Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 30 V VDGR Drain-gate Voltage (RGS = 20 k Ω) 30 V VGS Gate- source Voltage ± 16 V ID Drain Current (continuous) at TC = 25°C 8A ID Drain Current (continuous) at TC = 100°C 5A IDM( •) Drain Current (pulsed) 32 A Ptot Total Dissipation at TC = 25°C 2W INTERNAL SCHEMATIC DIAGRAM |
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