M68AW128ML

12/20

Write Mode

The M68AW128ML is in the Write mode whenever

the W and E are Low. Either the Chip Enable input

(E) or the Write Enable input (W) must be de-

asserted

during

Address

transitions

for

subsequent write cycles. When E (W) is Low, and

UB or LB is Low, write cycle begins on the W (E)’s

falling edge. When E and W are Low, and UB = LB

= High, write cycle begins on the first falling edge

of UB or LB. Therefore, address setup time is

referenced to Write Enable, Chip Enable or UB/LB

determined by the latter occurring edge.

The Write cycle can be terminated by the earlier

rising edge of E, W or UB/LB.

If the Output is enabled (E = Low, G = Low, LB or

UB = Low), then W will return the outputs to high

must be taken to avoid bus contention in this type

rising edge of UB/LB whichever occurs first, and

tively.

Figure 11. Write Enable Controlled, Write AC Waveforms

Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applioed.

AI04841

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A16

E

W

DQ0-DQ15

VALID

tAVWH

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

tBLWH

UB, LB

tELWH