AM6548BACDXEAF datasheet(261/282 Pages) TI

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9.2 Peripheral- and Interface-Specific Design Information

9.2.1 DDR Board Design and Layout Guidelines

The goal of the AM65x/DRA80xM DDR Board Design and Layout Guidelines is to make the DDR4 system

implementation straightforward for all designers. Requirements have been distilled down to a set of layout and

routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.

TI only supports board designs using DDR4 memories that follow the guidelines in this document.

9.2.2 OSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the OSPI interfaces.

9.2.2.1 No Loopback and Internal Pad Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450pS (~7cm

as stripline or ~8cm as microstrip)

• 50 Ω PCB routing is recommended along with series terminations, as shown in OSPI Interface High Level

Schematic

• Propagation delays and matching:

– A to B < 450ps

– Matching skew: < 60pS

MCU_OSPI[x]_CLK

OSPI/QSPI/SPI

device clock input

OSPI/QSPI/SPI

device IOy, CS#

MCU_OSPI[x]_D[y],

MCU_OSPI[x]_CSn[z]

OSPI_Board_01

*0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed

Figure 9-1. OSPI Interface High Level Schematic

9.2.2.2 External Board Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input

• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)

should be approximately equal to half of the signal propagation delay from the MCU_OSPI[x]_LBCLKO pin to

the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.

• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must

be approximately equal to the signal propagation delay of the control and data signals between the flash

device and the SoC device (E to F, or F to E)

• 50 Ω PCB routing is recommended along with series terminations, as shown in OSPI Interface High Level

Schematic

• Propagation delays and matching:

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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