AM6548BACDXEAF datasheet(258/282 Pages) TI

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through MCU_TIMER3 instances. System level muxes are used to control the capture source pin for each

MCU_TIMER[3-0] and the MCU_TIMER[3-0] source for each MCU_TIMER_IO[1-0] PWM output

In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM

outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER11 instances.

System level muxes are used to control the capture source pin for each TIMER[11-0] and the TIMER[11-0]

source for each TIMER_IO[7-0] PWM output.

For more information, see Timers section in the device TRM.

8.4.5.26 UART

The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There

are five UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function

clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral

devices or interprocessor communication between devices.

The CIR mode uses a variable pulse-width modulation (PWM) technique (based on multiples of a programmable

t period) to encompass the various formats of infrared encoding for remote-control applications. The CIR logic

transmits data packets based on a user-definable frame structure and packet content.

For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in the

device TRM.

8.4.5.27 USB

Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange

between a host device and a wide range of simultaneously accessible peripherals.

The device supports two USB subsystems, both instantiated in the MAIN system domain:

• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)

PHY and HS/FS/LS (USB2.0) PHY

• USB3SS1 is HighSpeed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS/LS

(USB2.0) PHY

For more information, see Universal Serial Bus (USB) Subsystem section in the device TRM.

8.5 Identification

8.5.1 Revision Identification

For more information about Revision Identification, see Section 10.1, Device Nomenclature.

8.5.2 Die Identification

The device part number identification data can be read in the CTRLMMR_WKUP_JTAG_DEVICE_ID register.

For more information about Die Identification, see Device Identification section in the device TRM.

8.5.3 JTAG Identification

The manufacturer identity, the boundary scan part number, and the silicon revision of the device can be read in

the CTRLMMR_WKUP_JTAGID register.

For more information about JTAG Identification, see Device Identification section in the device TRM.

8.5.4 ROM Code Identification

The ROM code uses several global memories in the MSRAM that are useful for debugging.

For more information about ROM Code Identification, see Global Memory Addresses Used by ROM Code

section in the device TRM.

AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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