AM6548BACDXEAF datasheet(255/282 Pages) TI

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control the state driven on the output pin. When configured as an input, user can obtain the state of the input by

reading the state of an internal register.

In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different

interrupt/event generation modes.

The device has three instances of GPIO modules. The GPIO pins are grouped into banks (16 pins per bank

and 9 banks per module), which means that each GPIO module provides up to 144 dedicated general-purpose

pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9

banks × 16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in

this device, general purpose interface supports up to 242 pins.

For more information, see General-Purpose Interface (GPIO) section in the device TRM.

8.4.5.13 GPMC

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external

memory devices like:

• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices

• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash

devices

• NAND flash

• Pseudo-SRAM devices

For more information, see General-Purpose Memory Controller (GPMC) section in the device TRM.

8.4.5.14 HyperBus

Note

HyperBus is not available on this device.

The HyperBus module is a part of the device Flash Subsystem (FSS).

The HyperBus module is a low pin count memory interface that provides high read/write performance. The

HyperBus module connects to HyperBus memory (HyperFlash or HyperRAM) and uses simple HyperBus

protocol for read and write transactions.

There is one HyperBus™ module inside the device. The HyperBus module includes one HyperBus Memory

Controller (HBMC).

For more information, see HyperBus Interface section in the device TRM.

8.4.5.15 I2C

The device contains six multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface

between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via the I2C serial

bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and

from the LH device through the 2-wire I2C interface.

Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.

The WKUP_I2C0 and MCU_I2C0 controllers have dedicated I2C compliant open drain buffers, and support fast

mode (up to 400 Kbps).The I2C0, I2C1, I2C2, and I2C3 controllers are multiplexed with standard LVCMOS I/O

and connected to emulate open drain.The I2C emulation is achieved by configuring the LVCMOS buffers to

output Hi-Z instead of driving high when transmitting logic 1.

For more information, see Inter-Integrated Circuit (I2C) Interface section in the device TRM.

8.4.5.16 MCAN

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed

real-time control. CAN has high immunity to electrical interference. In a CAN network, many short messages are

broadcast to the entire network, which provides for data consistency in every node of the system.

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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