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AM6548BACDXEAF Datasheet(PDF) 203 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 203 Page - Texas Instruments |
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203 / 282 page ![]() ASP8 ASP7 ASP4 ASP4 ASP3 ASP2 ASP2 ASP1 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 MCASP[x]_ACLKR/X (Falling Edge Polarity) MCASP[x]_AHCLKR/X (Rising Edge Polarity) MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay) MCASP[x]_AXR[x] (Data In/Receive) ASP6 ASP5 MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0) (A) MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1) (B) A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured for falling edge (to shift data in). B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured for rising edge (to shift data in). Figure 7-66. MCASP Input Timing www.ti.com AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: AM6548 AM6528 AM6526 |
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