AM6548BACDXEAF datasheet(206/282 Pages) TI

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Table 7-46. SPI Timing Conditions (continued)

PARAMETER

MIN

MAX

UNIT

Output load capacitance

7.9.5.15.1 SPI—Master Mode

Table 7-47, Table 7-48, Figure 7-68, Figure 7-69 present Timing Requirements and Switching Characteristics for

SPI - Master Mode.

Table 7-47. SPI Timing Requirements - Master Mode

NO.

MIN

MAX

UNIT

SM4

tsu(MISO-SPICLK)

Setup time, SPI_D[x] valid before SPI_CLK active edge

SM5

th(SPICLK-MISO)

Hold time, SPI_D[x] valid after SPI_CLK active edge

Table 7-48. SPI Switching Characteristics - Master Mode

NO.

DESCRIPTION

MODE

MIN

MAX

UNIT

SM1

tc(SPICLK)

Cycle time, SPI_CLK

20.8

SM2

tw(SPICLKL)

Typical Pulse duration, SPI_CLK low

-1 +

0.5P(1)

SM3

tw(SPICLKH)

Typical Pulse duration, SPI_CLK high

-1 +

0.5P(1)

SM6

td(SPICLK-SIMO)

Delay time, SPI_CLK active edge to SPI_D[x] transition

-3

SM7

tsk(CS-SIMO)

Delay time, SPI_CS[x] active to SPI_D[x] transition

SM8

td(SPICLK-CS)

Delay time, SPI_CS[x] active to SPI_CLK first edge

Master_PHA0_POL0;

Master_PHA0_POL1;

-4 + B(2)

Master_PHA1_POL0;

Master_PHA1_POL1;

-4 + A(3)

SM9

td(SPICLK-CS)

Delay time, SPI_CLK last edge to SPI_CS[x] inactive

Master_PHA0_POL0;

Master_PHA0_POL1;

-4 + A(3)

Master_PHA1_POL0;

Master_PHA1_POL1;

-4 + B(2)

(1)

P = SPICLK period

(2)

B = (TCS + .5) × TSPICLKREF x Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.

(3)

When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

When P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

www.ti.com

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