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AM6548BACDXEAF Datasheet(PDF) 209 Page - Texas Instruments |
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AM6548BACDXEAF Datasheet(HTML) 209 Page - Texas Instruments |
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209 / 282 page ![]() 7.9.5.15.2 SPI—Slave Mode Table 7-49, Table 7-50, Figure 7-70and Figure 7-71 present Timing Requirements and Switching Characteristics for SPI - Slave Mode. Table 7-49. SPI Timing Requirements - Slave Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SS1 tc(SPICLK) Cycle time, SPI_CLK 20.8 ns SS2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.45P(1) ns SS3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.45P(1) ns SS4 tsu(SIMO-SPICLK) Setup time, SPI_D[x] valid before SPI_CLK active edge 5 ns SS5 th(SPICLK-SIMO) Hold time, SPI_D[x] valid after SPI_CLK active edge 5 ns SS8 tsu(CS-SPICLK) Setup time, SPI_CS[x] valid before SPI_CLK first edge 5 ns SS9 th(SPICLK-CS) Hold time, SPI_CS[x] valid after SPI_CLK last edge 5 ns Table 7-50. SPI Switching Characteristics - Slave Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SS6 td(SPICLK-SOMI) Delay time, SPI_CLK active edge to mcspi_somi transition 2 5 ns SS7 tsk(CS-SOMI) Delay time, SPI_CS[x] active edge to mcspi_somi transition 20.95 ns (1) P = SPICLK period. www.ti.com AM6548, AM6528, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: AM6548 AM6528 AM6526 |
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