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STM32F071X8 Datasheet(PDF) 86 Page - STMicroelectronics |
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STM32F071X8 Datasheet(HTML) 86 Page - STMicroelectronics |
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86 / 122 page ![]() Electrical characteristics STM32F071x8 STM32F071xB 86/122 DS10009 Rev 7 6.3.17 DAC electrical specifications Table 60. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage for DAC ON 2.4 - 3.6 V - RLOAD(1) Resistive load with buffer ON 5- - kΩ Load connected to VSSA 25 - - kΩ Load connected to VDDA RO(1) Impedance output with buffer OFF -- 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(1) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT min(1) Lower DAC_OUT voltage with buffer ON 0.2 - - V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VDDA = 3.6 V and (0x155) and (0xEAB) at VDDA = 2.4 V DAC_OUT max(1) Higher DAC_OUT voltage with buffer ON -- VDDA – 0.2 V DAC_OUT min(1) Lower DAC_OUT voltage with buffer OFF -0.5 - mV It gives the maximum output excursion of the DAC. DAC_OUT max(1) Higher DAC_OUT voltage with buffer OFF -- VDDA – 1LSB V IDDA(1) DAC DC current consumption in quiescent mode(2) -- 600 µA With no load, middle code (0x800) on the input -- 700 µA With no load, worst code (0xF1C) on the input DNL(3) Differential non linearity Difference between two consecutive code-1LSB) -- ±0.5 LSB Given for the DAC in 10-bit configuration -- ±2 LSB Given for the DAC in 12-bit configuration INL(3) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) -- ±1 LSB Given for the DAC in 10-bit configuration -- ±4 LSB Given for the DAC in 12-bit configuration Offset(3) Offset error (difference between measured value at Code (0x800) and the ideal value = VDDA/2) -- ±10 mV - -- ±3 LSB Given for the DAC in 10-bit at VDDA = 3.6 V -- ±12 LSB Given for the DAC in 12-bit at VDDA = 3.6 V |
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