STM32F071X8 datasheet(17/122 Pages) STMICROELECTRONICS

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DS10009 Rev 7

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STM32F071x8 STM32F071xB

Functional overview

Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL

input source. This oscillator can be automatically fine-trimmed by the means of the CRS

peripheral using the external synchronization.

3.7

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to

avoid spurious writing to the I/Os registers.

3.8

Direct memory access controller (DMA)

The 7-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory

and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code

intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers

(except TIM14), DAC and ADC.

3.9

Interrupts and events

3.9.1

Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M0) and 4

priority levels.

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Closely coupled NVIC core interface

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail-chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

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