BT817AQ-R datasheet(27/58 Pages) BRIDGETEK

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BT817A Automotive Advanced Video Engine Datasheet

Version 1.0

Document No.: BRT_000251 Clearance No.: BRT#194

REG_VSYNC0

TVF

Vertical Front Porch (in lines)

REG_VSYNC1

TVF + TVP

Vertical Front Porch plus Vsync Pulse width (in lines)

Table 4-14 Registers for RGB Horizontal and Vertical Timings

When setting the display registers, ensure that the following conditions are met:

HOFFSET < (HCYCLE – HSIZE)

VOFFSET < (VCYCLE – VSIZE)

Figure 4-6 RGB Timing Waveforms

BT817A supports adaptive HSYNC and adaptive framerate operations. In adaptive HSYNC mode the

graphics engine may delay the start of the scanout line up to the cycle count given in

REG_AH_HCYCLE_MAX, while keeping PCLK running. Adaptive HSYNC is enabled when

REG_AH_HCYCLE_MAX is set to a non-zero value between REG_HCYCLE and 4095. In adaptive

framerate mode the graphics engine may suspend PLCK if the next scanout line is not ready. Note

that some displays (for example displays with LVDS interface) may not support PCLK varying or

pausing. If not supported, disable adaptive framerate via register REG_ADAPTIVE_FRAMERATE.

BT817A supports Horizontal Scanout Filter (HSF) operation. The HSF applies a high-quality filter to

output pixels, correcting for LCD panels with non-square pixels (the physical size of the LCD pixel is

not square). HSF is enabled and disabled with CMD_HSF. Note that HSF and 2X are not supported

together.

Table 4-15 lists all the supported display modes for the RGB interface.

EXTSYNC

adaptive

HSF

Description

passthrough mode

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