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BT817AQ-R Datasheet(PDF) 47 Page - Bridgetek Pte Ltd. |
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BT817AQ-R Datasheet(HTML) 47 Page - Bridgetek Pte Ltd. |
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47 / 58 page ![]() Copyright © Bridgetek Pte Ltd 47 BT817A Automotive Advanced Video Engine Datasheet Version 1.0 Document No.: BRT_000251 Clearance No.: BRT#194 6.4.3 RGB Interface Timing Parameter Description Value Units Min Typ Max Tpclk Pixel Clock period 10.4 ns Td Output delay relative to PCLK rising edge (REG_PCLK_POL=1) or falling edge (REG_PCLK_POL=0). Applied for all the RGB output pins. 4 Ns Th Output hold time relative to PCLK rising edge (REG_PCLK_POL=1) or falling edge (REG_PCLK_POL=0). Applied for all the RGB output pins. 0.5 Ns Table 6-10 RGB Interface Timing Characteristics Figure 6-2 RGB Interface Timing |
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