7 Detailed Description

7.1 Overview

The LM2105 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel

FETs in a synchronous buck or a half-bridge configuration. The two outputs are independently controlled with

two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as

long as the signals meet the turn-on and turn-off threshold specifications of the LM2105. The floating high-side

driver is capable of working with a BST voltage up to 105 V. A bootstrap diode is integrated in the LM2105

device to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while

consuming low power and providing clean level transitions from the control logic to the high-side gate driver.

Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails.

7.2 Functional Block Diagram

LEVEL

SHIFT

UVLO

UVLO

INH

INL

GVDD

BST

GH

SH

GL

GND

DRIVER

STAGE

DRIVER

STAGE

7.3 Feature Description

7.3.1 Start-Up and UVLO

Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply

voltage (VGVDD) and the bootstrap capacitor voltage (VBST-SH). The UVLO circuit inhibits each output until

sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents

chattering during supply voltage variations. When the supply voltage is applied to the GVDD pin of the device,

both outputs are held low until VGVDD exceeds the UVLO threshold, typically 4.6 V. Any UVLO condition on the

bootstrap capacitor (VBST–SH) disables only the high-side output (GH).

Table 7-1. GVDD UVLO Logic Operation

CONDITION (VBST- SH > VBSTR)

INH

INL

GH

GL

VGVDD – GND < VGVDDR during device start-up

H

L

L

L

L

H

L

L

H

H

L

L

L

L

L

L

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LM2105

SNVSCB0A – JANUARY 2023 – REVISED MARCH 2023

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