Table 7-1. GVDD UVLO Logic Operation (continued)

CONDITION (VBST- SH > VBSTR)

INH

INL

GH

GL

VGVDD – GND < VGVDDR – VDDHYS after device start-up

H

L

L

L

L

H

L

L

H

H

L

L

L

L

L

L

Table 7-2. BST UVLO Logic Operation

CONDITION (VGVDD > VGVDDR)

INH

INL

GH

GL

VBST-SH < VBSTR during device start-up

H

L

L

L

L

H

L

H

H

H

L

H

L

L

L

L

VBST-SH < VBSTR – VBSTHYS after device start-up

H

L

L

L

L

H

L

H

H

H

L

H

L

L

L

L

7.3.2 Input Stages

The INL and INH inputs operate independent of each other. There is no fixed time de-glitch filter implemented

at the inputs and therefore propagation delay and delay matching are not sacrificed. In other words, there is

no built-in dead time. If the dead time between two outputs is desired then that shall be programmed through

the microcontroller. A small filter at each of the inputs of the driver further improves system robustness in

noise-prone applications. The inputs have internal pulldown resistors with typical value of 200 kΩ. Thus, when

the inputs are floating, the outputs are held low.

7.3.3 Level Shift

The level shift circuit is the interface from the high-side input, which is a GND referenced signal, to the high-side

driver stage, which is referenced to the switch node (SH). The level shift allows control of the GH output which is

referenced to the SH pin and provides excellent delay matching with the low-side driver.

7.3.4 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,

and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The

low-side output stage is referenced to GND and the high-side is referenced to SH.

7.3.5 SH Transient Voltages Below Ground

In most applications, the body diode of the external low-side power MOSFET clamps the SH node to ground.

In some situations, board capacitance and inductance can cause the SH node to transiently swing several volts

below ground, before the body diode of the external low-side MOSFET clamps this swing. The SH pin in the

LM2105 is allowed to swing below ground as long as specifications are not violated and conditions mentioned in

this section are followed.

SH must always be at a lower potential than GH. Pulling GH more negative than specified conditions can

activate parasitic transistors which may result in excessive current flow from the BST supply. This may result

in damage to the device. The same relationship is true with GL and GND. If necessary, a Schottky diode can

be placed externally between GH and SH or GL and GND to protect the device from this type of transient. The

diode must be placed as close to the device pins as possible in order to be effective.

Low ESR bypass capacitors from BST to SH and from GVDD to GND are essential for proper operation of the

gate driver device. The capacitor should be located at the leads of the device to minimize series inductance.

The peak currents from GL and GH can be quite large. Any series inductance with the bypass capacitor causes

voltage ringing at the leads of the device which must be avoided for reliable operation.

LM2105

SNVSCB0A – JANUARY 2023 – REVISED MARCH 2023

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