5 Pin Configuration and Functions

BST

GH

SH

GL

GVDD

INH

INL

GND

Not to scale

1

2

3

4

5

6

7

8

Figure 5-1. D Package, 8-Pin SOIC (Top View)

1

2

3

4

5

6

7

8

GVDD

INH

INL

GND

BST

GH

SH

GL

Not to scale

Thermal

Pad

Figure 5-2. DSG Package, 8-Pin WSON (Top View)

Table 5-1. Pin Functions

PIN

DESCRIPTION

NO.(1)

NAME

TYPE(2)

1

GVDD

P

Gate driver positive supply rail. Locally decouple to ground using low ESR and ESL capacitor

located as close to IC as possible.

2

INH

I

High-side control input. The INH input is compatible with TTL and CMOS input thresholds.

Unused INH input must be tied to ground and not left open.

3

INL

I

Low-side control input. The INL input is compatible with TTL and CMOS input thresholds.

Unused INL input must be tied to ground and not left open.

4

GND

G

Ground. All signals are referenced to this ground.

5

GL

O

Low-side gate driver output. Connect to the gate of the low-side MOSFET or one end of

external gate resistor, when used.

6

SH

P

High-side source connection. Connect to the negative terminal of the bootstrap capacitor and

to the source of the high-side MOSFET.

7

GH

O

High-side gate driver output. Connect to the gate of the high-side MOSFET or one end of

external gate resistor, when used.

8

BST

P

High-side gate driver positive supply rail. Connect the positive terminal of the bootstrap

capacitor to BST and the negative terminal of the bootstrap capacitor to SH. The bootstrap

capacitor must be placed as close to IC as possible.

(1)

For 8-pin WSON package, TI recommends that the exposed pad on the bottom of the package be soldered to ground plane on the

PCB and the ground plane must extend out from underneath the package to improve heat dissipation.

(2)

G = Ground, I = Input, O = Output, and P = Power

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LM2005

SNVSCB6B – FEBRUARY 2023 – REVISED SEPTEMBER 2023

Copyright © 2023 Texas Instruments Incorporated

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