LTC3217

11

3217f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

At moderate to high output power, the quiescent current

of the LTC3217 is negligible and the expression shown in

Equation 6 is valid.

Once dropout is detected at the LED pin, the LTC3217

enables the charge pump in 1.5x mode.

In 1.5x boost mode, the efficiency is similar to that of a

linear regulator with an effective input voltage of 1.5 times

the actual input voltage. This is because the input current

for a 1.5x charge pump is approximately 1.5 times the load

current. In an ideal 1.5x charge pump, the power

efficiency would be given by:

η

IDEAL

LED

IN

LED

LED

BAT

LED

LED

BAT

P

P

VI

VI

V

V

==

=

(•

)

(• ( . ) •

)

( . •)

15

15

(7)

Similarly, in 2x boost mode, the efficiency is similar to that

of a linear regulator with an effective input voltage of 2

times the actual input voltage. In an ideal 2x charge pump,

the power efficiency would be given by:

η

IDEAL

LED

IN

LED

LED

BAT

LED

LED

BAT

P

P

VI

VI

V

V

==

=

(•

)

(• ( ) •

)

( •)

22

(8)

Thermal Management

For higher input voltages and maximum output current,

there can be substantial power dissipation in the LTC3217.

If the junction temperature increases above approxi-

mately 150

°C the thermal shutdown circuitry will auto-

matically deactivate the output current sources and charge

pump. To reduce maximum junction temperature, a good

thermal connection to the PC board is recommended.

Connecting the Exposed Pad to a ground plane and

maintaining a solid ground plane under the device will

reduce the thermal resistance of the package and PC

board considerably.

APPLICATIO S I FOR ATIO

PACKAGE DESCRIPTIO

UD Package

16-Lead Plastic QFN (3mm

× 3mm)

(Reference LTC DWG # 05-08-1691)

3.00

± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40

± 0.10

BOTTOM VIEW—EXPOSED PAD

1.45

± 0.10

(4-SIDES)

0.75

± 0.05

R = 0.115

TYP

0.25

± 0.05

1

PIN 1 NOTCH R = 0.20 TYP

OR 0.25

× 45° CHAMFER

15

16

2

0.50 BSC

0.200 REF

0.00 – 0.05

(UD16) QFN 0904

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.45

± 0.05

(4 SIDES)

2.10

± 0.05

3.50

± 0.05

0.70

±0.05

0.25

±0.05

0.50 BSC

PACKAGE

OUTLINE