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12/04

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Power Integrations

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are trademarks of Power Integrations. Copyright 2004, Power Integrations

Power Integrations may make changes to its products at any time. Power Integrations has no liability arising from your use of any information, device or circuit described

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• At zero load, maximum input voltage, the bias voltage

across C4 should be

≥8 V (12 V to 15 V under nominal

conditions).

• Good layout practices should be followed:

- Locate C5, C6 and R4 close to U1 with grounds returned

to the SOURCE pin.

- Primary return should be connected to the DPA-Switch

tab, not the SOURCE pin.

- Minimize the primary and secondary loop areas to

reduce parasitic leakage inductance.

• Consult AN-31 for additional design tips and information.

• Choose C17 to provide adequate gate charge to Q2 at low

line (typically 5 V) and to limit Q2 gate to a safe voltage at

high line (typically less than 20 V).

Core

Bobbin

Winding Detail

Winding Order

(pin numbers)

Inductance

Primary Resonant

Frequency

TRANSFORMER PARAMETERS

EFD20 Ungapped

Ferroxcube EFD20-3F3

EFD20 10 pin

(B&B B-052 or equivalent)

Primary: 8T + 8T, 25 AWG

Secondary: 4T, 0.002" Cu Foil

Primary (5-3), tape,

Secondary (6,7-9,10), tape,

Primary (3-1), tape

Primary: 307 µH ±25%, Leakage: 1 µH (max.)

3 MHz (minimum)

Core

Winding Details

Bobbin

Winding Order

(pin numbers)

Inductance

OUTPUT INDUCTOR PARAMETERS

RM6ILP

Ferroxcube 3F3 material

Gap for A

2

Main: 6T, 4x26 AWG

Bias: 15T, 32 AWG

RM6ILP 8 pin

(EPCOS B-65821-A6008-T1 or equivalent)

Bias (1-2), tape,

Main Winding (7,8-5,6), tape

8 µH ±10%

Table 2. Output Inductor Construction Information.

Table 1. Transformer Construction Information.

010

15

20

25

530

Output Power (W)

70

60

50

80

90

100

V

V

V

Figure 2. DPA-Switch 30 W, 5 V Synchronous

Rectifier Efficiency vs. Output Power.