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Design Idea DI-25

with Synchronous Rectification

December 2004

DI-25

®

Application

DC-DC Converter

DPA425R

5 V

Power Output

30 W

Input Voltage

Output Voltage

Topology

Device

36-75 VDC

Forward

Figure 1. DPA-Switch 30 W, 5 V, 6 A DC-DC Converter.

Design Highlights

• Extremely low component count

• High Efficiency – 90% using synchronous rectification

• Accurate UV/OV allows self-driven synchronous

rectification

• No current sense resistor or current transformer required

• Output overload, open loop and thermal protection

• 300 kHz switching frequency – optimizes efficiency when

simple self-driven synchronous rectification is used

Operation

DPA-Switch greatly simplifies the deisign compared to a discrete

implementation. Resistor R1 programs the input under/over

voltages to 33 V and 86 V, respectively, and linearly reduces the

maximumdutycyclewithinputvoltagetopreventcoresaturation

during load transients. Tight tolerances of the UV/OV thresholds

determine the secondary MOSFETs gate voltage range, allowing

low cost, self-driven synchronous rectification. Resistor R3

programs the internal current limit of the DPA425R to 45% of

nominal. The larger DPA-Switch selection reduces conduction

losses, raising efficiency without design or overload penalty.

DRAIN voltage clamping and core reset is provided by VR1

and the gate capacitance of Q1. The bias supply for U1 is

generated from an auxiliary winding on L2, providing higher

efficiency than a winding on T1.

Capacitor C17 and R15 drive the gate of Q2, C17 providing DC

isolation to prevent Q1 gate overstress during power down.

Diode D4 resets the voltage on C17 before the next switching

cycle. Resistor R17 filters voltage spikes at the gate of Q1 and

D2 prevents the body diode of Q1 from conducting. MOSFETs

Q1 and Q2 are connected as self-driven synchronous rectifiers.

Key Design Points

• For nominal undervoltage set point V

R1 = (V

• Select time constant of R16 and C17 to be much longer than

the period of one switching cycle.

• Zener VR1 safely limits the DRAIN voltage below BV

DSS

and guarantees transformer reset.

• Opto U2 should have a CTR range of 100% to 200% for

optimum loop stability.

U1

DPA425R

D1

BAV

19WS

D2

C5

220 nF

VR1

SMBJ

150

C6

68 µF

10 V

C7

1 nF

1.5 kV

R14

10 Ω

T1

R3

18.2 kΩ

1%

R1

619 kΩ

1%

R4

1.0 Ω

C10

100 µF

10 V

C11

100 µF

10 V

C12

1 µF

10 V

36-75 VDC

L1

1 µH

2.5 A

L2

C1, C2 & C3

1 µF

100 V

DL

SX

F

C

CONTROL

CONTROL

U2

PC357N1T

PI 3472 040903

DPA-Switch

5 V, 6 A

RTN

Q2

Si4888

DY

R15

10 Ω

R16

10 kΩ

D4

BAV19WS

R17

10 Ω

Q1

Si4888

DY

C4

4.7 µF

20 V

U2

D3

BAV19WS

U3

LM431AIM3

R9

220 Ω

R11

10.0 kΩ

1%

R10

10.0 kΩ

1%

R12

5.1 Ω

R7

10 kΩ

C14

1 µF

C13

10 µF

10 V

C16

100 nF

R6

150 Ω

V

IN

+

V

IN

C17

3300 pF