MCP1725-1202ESLASHSN datasheet(18/32 Pages) MICROCHIP

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MCP1725

DS22026A-page 18

4.6

CDELAY Input

The CDELAY input is used to provide the power-up

delay timing for the power good output, as discussed in

the previous section. By adding a capacitor from the

CDELAY pin to ground, the PWRGD power-up time

delay can be adjusted from 200 µs (no capacitance on

CDELAY) to 300 ms (0.1 µF of capacitance on CDELAY).

See Section 1.0 “Electrical Characteristics” for

CDELAY timing tolerances.

Once the power good threshold (rising) has been

reached, the CDELAY pin charges the external capacitor

to VIN. The charging current is 140 nA (typical). The

PWRGD output will transition high when the CDELAY

pin voltage has charged to 0.42V. If the output falls

below the power good threshold limit during the

charging time between 0.0V and 0.42V on the CDELAY

pin, the CDELAY pin voltage will be pulled to ground,

thus resetting the timer. The CDELAY pin will be held low

until the output voltage of the LDO has once again risen

above the power good rising threshold. A timing

diagram showing CDELAY, PWRGD and VOUT is shown

in Figure 4-4.

FIGURE 4-4:

CDELAY and PWRGD Timing

Diagram.

4.7

Shutdown Input (SHDN)

The SHDN input is an active-low input signal that turns

the LDO on and off. The SHDN threshold is a

percentage of the input voltage. The typical value of

this shutdown threshold is 30% of VIN, with minimum

and maximum limits over the entire operating

temperature range of 45% and 15%, respectively.

The SHDN input will ignore low-going pulses (pulses

meant to shut down the LDO) that are up to 400 ns in

pulse width. If the shutdown input is pulled low for more

than 400 ns, the LDO will enter Shutdown mode. This

small bit of filtering helps to reject any system noise

spikes on the shutdown input signal.

On the rising edge of the SHDN input, the shutdown

circuitry has a 30 µs delay before allowing the LDO

output to turn on. This delay helps to reject any false

turn-on signals or noise on the SHDN input signal. After

the 30 µs delay, the LDO output enters its soft-start

period as it rises from 0V to its final regulation value. If

the SHDN input signal is pulled low during the 30 µs

delay period, the timer will be reset and the delay time

will start over again on the next rising edge of the

SHDN input. The total time from the SHDN input going

high (turn-on) to the LDO output being in regulation is

typically 100 µs. See Figure 4-5 for a timing diagram of

the SHDN input.

FIGURE 4-5:

Shutdown Input Timing

Diagram.

VOUT

TPG

VPWRGD_TH

CDELAY

CDELAY Threshold (0.42V)

PWRGD

VIN (typ)

SHDN

VOUT

30 µs

70 µs

TOR

400 ns (typ)

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