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Copyright © 2006 Active-Semi, Inc.

ACT4072

Stability compensation

The feedback system of the IC is stabilized by the

components at the COMP pin, as shown in Figure

2. The DC loop gain of the system is determined by

the following equation:

COMP

VEA

OUT

VDC

G

A

I

V

222

.

1

A



COMP

VEA

EA

1

P

C

A

2

G

f





COMP

COMP

1

Z

C

R

2

1

f





COMP2

COMP

3

P

C

R

2

1

f





Follow the following steps to compensate the IC:

STEP 1. Set the cross over frequency at 1/10 of the

OUT

OUT

OUT

2

P

C

V

2

I

f





The second pole P2 is the output pole:

OUT

OUT

5

COMP

C

V

10

x

3

.

1

C





STEP 3. If the output capacitor’s ESR is high

enough to cause a zero at lower than 4 times the

cross over frequency, an additional compensation

V

012

.

0

,

C

10

x

1

.

1

Min

R

OUT

OUT

6

ESROUT

















COMP

ESROUT

OUT

2

COMP

R

R

C

C



stability against PCB layout parasitic effects.

Table 2 shows some calculated results based on the

compensation method above.

Table 2:

Typical Compensation for Different Output volt-

ages and Output Capacitors



2.5V

22

μF Ceramic

8.2k

Ω

2.2nF

100pF

3.3V

22

μF Ceramic

12k

Ω

1.5nF

100pF

5V

22

μF Ceramic

15k

Ω

1.5nF

100pF

2.5V

47

μF SP CAP

15k

Ω

1.5nF

100pF

3.3V

47

μF SP CAP

15k

Ω

1.8nF

100pF

5V

47

μF SP CAP

15k

Ω

2.7nF

100pF

2.5V

470µF/6.3V/30m

Ω

15k

Ω

15nF

1nF

3.3V

470µF/6.3V/30m

Ω

15k

Ω

22nF

1nF

5V

470µF/6.3V/30m

Ω

15k

Ω

27nF

1nF

OUT

OUT

8

COMP

EA

SW

OUT

OUT

COMP

C

V

10

x

3

.

2

V

222

.

1

G

G

10

f

C

V

2

R







(10)

(12)

(11)

(13)

(4)

(5)

(6)

(7)

(8)

(

Ω)

(9)

(Ω)

(F)

(F)

: C

capacitor.

: C

parasitics

Figure 2:

Stability Compensation

Figure 3 shows an example ACT4072 application

circuit generating a 5V/2A output.

COMP

5

COMP

R

10

8

.

1

C





