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SLAS366 Datasheet(PDF) 19 Page - Texas Instruments |
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SLAS366 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 58 page  3–7 1. FS = MCLK/(16xMxNxP) 2. FS = n1 x fs1 (n1 = 1,2, 0, 8 defined in the control register 3 of CODEC1) 3. FS = n2 x fs2 (n2 = 1,2, 0, 8 defined in the control register 3 of CODEC2) For validating the conversion data from this operation: For DAC: DSP need to give same data for n1 samples. CODEC1 picks one of n1 samples. For ADC: CODEC1 gives same data for n1 samples. DSP should pick one of n1 samples. SCLK FSD (Output) DIN/DOUT (16 Bit) MSB LSB D15 D14 D1 D0 0 1 14 15 13 D15 FS 16 SCLKs Figure 3–6. Timing Diagram for FSD Output MCLK DIN DOUT FS SCLK MCLK DIN DOUT FS SCLK MCLK DIN DOUT FS SCLK Slave 2 Slave 1 Slave 0 Master MCLK DIN DOUT FSD SCLK FSD FSD FS CLKOUT DX DR FSX FSR CLKX CLKR TMS320C5x M/S M/S M/S M/S FSD IOVDD 1 k Ω 100 MHz Max IOVDD Figure 3–7. Cascade Connection (To DSP Interface) |
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