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SLAS366 Datasheet(PDF) 21 Page - Texas Instruments

Part # SLAS366
Description  Low Power CMOS, 16-Bit, 26-KSPS Codec With Smart Time Division Multiplexed (SMARTDM™) Serial Port
PDF  58 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

SLAS366 Datasheet(HTML) 21 Page - Texas Instruments

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3–9
3.7.1
S2C (Start-Stop Communication)
The S2C is a write-only interface selected by programming bits D1-D0 of control register 2 to 01. The SDA input is
normally in a high state, pulled low (START bit) to start the communication, and pulled high (STOP bit) after the
transmission of the LSB. Figure 3–9 shows the timing diagram of S2C. The S2C also supports a broadcast mode in
which the same register of all devices in cascade is programmed in a single write. To use S2Cs broadcast mode,
execute the following steps:
1.
Write 111 1000 1111 1111 after the start bit to enable the broadcast mode.
2.
Write data to program control register as specified in with bits D14–D11 = XXXX (don’t care).
3.
Write 111 1000 0000 0000 after the start bit to disable the broadcast mode.
D15
D14
D13
D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCL
SDA
Start Bit = 0
Stop Bit = 1
SMARTDM Device
Address
(see Table 3–1)
Register
Address
Register Content
Figure 3–9. S2C Programming
3.7.2
I2C
Each I2C read-from or write-to AIC14s control register is given by index register address.
Read/write sequence always starts with the first byte as I2C address followed by 0. During the second byte,
default/broadcast mode is set and the index register address is initialized. For write operation control
register, data to be written is given from the third byte onwards. For read operation, stop-start is performed
after the second byte. Now the first byte is I2C address followed by 1. From the second byte onwards, control
register data appears.
Each time read/write is performed, the index register address is incremented so that next read/write is
performed on the next control register.
During the first write cycle and all write cycles in the broadcast, only the device with address 0000 issues
ACK to the I2C.
I2C Write Sequence
SCL
SDA
A5
A4
A3
A2
A1
A0
0
ACK B7
B6
B5
B4
B3
R2
R1
R0
A6
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ACK
ACK
ACK
Start Bit = 0
SMARTDM Device
Address
(see Table 3-1)
00000 = Default
11111 = Broadcast Mode
Index Register Address
(Index)
Control Register Data for Write
(Index)
Control Register Data for Write
(Index+1)
6
Programmable I2C Device Address
Set by Control Register 2
I2C
5
I2C
4
I2C
Figure 3–10. I2C Write Sequence



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