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PSD913F2 Datasheet(PDF) 80 Page - STMicroelectronics |
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PSD913F2 Datasheet(HTML) 80 Page - STMicroelectronics |
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80 / 94 page  PSD9XX Family Preliminary Information 76 -12 -15 -20 Symbol Parameter Conditions Min Max Min Max Min Max Unit tISCCF TCK Clock Frequency (except for PLD) (Note 1) 12 10 9 MHz tISCCH TCK Clock High Time (Note 1) 40 45 51 ns tISCCL TCK Clock Low Time (Note 1) 40 45 51 ns tISCCF-P TCK Clock Frequency (for PLD only) (Note 2) 2 2 2 MHz tISCCH-P TCK Clock High Time (for PLD only) (Note 2) 240 240 240 ns tISCCL-P TCK Clock Low Time (for PLD only) (Note 2) 240 240 240 ns tISCPSU ISC Port Set Up Time 12 13 15 ns tISCPH ISC Port Hold Up Time 5 5 5 ns tISCPCO ISC Port Clock to Output 30 36 40 ns tISCPZV ISC Port High-Impedance to Valid Output 30 36 40 ns tISCPVZ ISC Port Valid Output to High-Impedance 30 36 40 ns ISC Timing (3 V Versions) NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode. 2. For program or erase PLD only. Symbol Parameter Min Typ Max Unit Flash Bulk Erase (Preprogrammed to 00) (Note 1) 3 30 sec Flash Bulk Erase (Not Preprogrammed) 5 sec tWHQV3 Sector Erase (Preprogrammed to 00) 1 30 sec tWHQV2 Sector Erase (Not Preprogrammed) 2.2 sec tWHQV1 Byte Program 14 1200 µs Program/Erase Cycles (Per Sector) 100,000 cycles tWHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output (DQ7-0) Valid (Data Polling) (Note 2) 30 ns Flash Program, Write and Erase Times (3 V Versions) NOTE: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data byte DQ0-7 is valid for reading. Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) |
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