ADSP-CM409F datasheet(13/124 Pages) AD

13 / 124 page

Rev. A

Page 13 of 124

November 2015

ADSP-CM402F/CM403F/CM407F/CM408F/CM409F

The GP counter can also support a programmable M/N fre-

quency scaling of the CNT_CUD and CNT_CDG pins onto

output pins in quadrature encoding mode.

Internal signals forwarded to each general-purpose timer enable

these timers to measure the intervals between count events.

Boundary registers enable auto-zero operation or simple system

warning by interrupts when programmable count values are

exceeded.

Serial Peripheral Interface Ports (SPI)

The processor contains the SPI-compatible port that allows the

processor to communicate with multiple SPI-compatible

devices.

In its simplest mode, the SPI interface uses three pins for trans-

ferring data: two data pins master output-slave input and master

input-slave output (SPI_MOSI and SPI_MISO) and a clock pin,

SPI_CLK. A SPI chip select input pin (SPI_SS) lets other SPI

devices select the processor, and three SPI chip select output

pins (SPI_SELn) let the processor select other SPI devices. The

SPI select pins are reconfigured general-purpose I/O pins. Using

these pins, the SPI provides a full-duplex, synchronous serial

interface, which supports both master and slave modes and

multimaster environments.

In a multimaster or multislave SPI system, the MOSI and MISO

data output pins can be configured to behave as open drain out-

puts (using the ODM bit) to prevent contention and possible

damage to pin drivers. An external pull-up resistor is required

on both the MOSI and MISO pins when this option is selected.

When ODM is set and the SPI is configured as a master, the

MOSI pin is three-stated when the data driven out on MOSI is a

logic high. The MOSI pin is not three-stated when the driven

data is a logic low. Similarly, when ODM is set and the SPI is

configured as a slave, the MISO pin is three-stated if the data

driven out on MISO is a logic high.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has integrated DMA channels for both

transmit and receive data streams.

Universal Asynchronous Receiver/Transmitter Ports

(UART)

The processor provides full-duplex universal asynchronous

receiver/transmitter (UART) ports, which are fully compatible

with PC-standard UARTs. Each UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. A UART port includes support for five to eight data bits,

and none, even, or odd parity. Optionally, an additional address

bit can be transferred to interrupt only addressed nodes in

multi-drop bus (MDB) systems. A frame is terminated by one,

one and a half, two or two and a half stop bits.

The UART ports support automatic hardware flow control

through the clear to send (CTS) input and request to send (RTS)

output with programmable assertion FIFO levels.

To help support the local interconnect network (LIN) protocols,

a special command causes the transmitter to queue a break

command of programmable bit length into the transmit buffer.

Similarly, the number of stop bits can be extended by a pro-

grammable inter-frame space.

The capabilities of the UARTs are further extended with sup-

port for the infrared data association (IrDA

®) serial infrared

physical layer link specification (SIR) protocol.

2-Wire Controller Interface (TWI)

The processor includes a 2-wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI module is compatible with the

widely used I2C bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation and

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400k bits/sec. The TWI interface pins are compati-

ble with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

Controller Area Network (CAN)

The CAN controller implements the CAN 2.0B (active) proto-

col. This protocol is an asynchronous communications protocol

used in both industrial and automotive control systems. The

CAN protocol is well suited for control applications due to its

capability to communicate reliably over a network. This is

because the protocol incorporates CRC checking, message error

tracking, and fault node confinement.

The CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-

rable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended

(29-bit) identifier (ID) message formats.

• Support for remote frames.

• Active or passive network support.

•Interrupts, including: TX complete, RX complete, error

and global.

An additional crystal is not required to supply the CAN clock, as

the CAN clock is derived from a system clock through a pro-

grammable divider.

10/100 Ethernet MAC (EMAC)

The processor can directly connect to a network by way of an

embedded fast Ethernet media access controller (MAC) that

supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M

bits/sec) operation. The 10/100 Ethernet MAC peripheral on the

processor is fully compliant to the IEEE 802.3-2002 standard. It

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