M48T212V-85MH1E datasheet(15/35 Pages) STMICROELECTRONICS

15 / 35 page

M48T212V

Operation

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making the final choice of an SRAM to use. The SRAM must be designed in a way where

the chip enable input disables all other inputs to the SRAM. This allows inputs to the

M48T212V and SRAMs to be “Don't care” once VCC falls below VPFD(min). The SRAM

should also guarantee data retention down to VCC = 2.0V. The chip enable access time must

be sufficient to meet the system needs with the chip enable output propagation delays

included.

If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT.

If data retention lifetime is a critical parameter for the system, it is important to review the

data retention current specifications for the particular SRAMs being evaluated. Most SRAMs

specify a data retention current at 3.0V. Manufacturers generally specify a typical condition

for room temperature along with a worst case condition (generally at elevated

temperatures). The system level requirements will determine the choice of which value to

use.

The data retention current value of the SRAMs can then be added to the IBAT value of the

M48T212V to determine the total current requirements for data retention. The available

battery capacity for the SNAPHAT® of your choice can then be divided by this current to

determine the amount of data retention available (see Table 20 on page 33).

For a further more detailed review of lifetime calculations, please see Application Note

AN1012.

M48T212V-85MH1E Datasheet(PDF) 15 Page - STMicroelectronics