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EPA030D Datasheet(PDF) 1 Page - Excelics Semiconductor, Inc. |
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EPA030D Datasheet(HTML) 1 Page - Excelics Semiconductor, Inc. |
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1 / 2 page  EPA030D UPDATED 11/30/2004 High Performance Heterojunction Dual-Gate FET Specifications are subject to change without notice. Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085 page 1 of 2 Phone: 408-737-1711 Fax: 408-737-1868 Web: www.excelics.com Revised December 2004 Chip Thickness: 75 ± 13 microns All Dimensions In Microns FEATURES • +18.0 dBm OUTPUT POWER AT 1dB COMPRESSION • 19.5 dB POWER GAIN AT 12GHz • 0.3 x 300 MICRON RECESSED “MUSHROOM” DUAL GATE • Si3N4 PASSIVATION • ADVANCED EPITAXIAL DOPING PROFILE PROVIDES EXTRA HIGH PERFORMANCE AND HIGH RELIABILITY • MIXER, SWITCH, AGC AND TEMPERATURE COMPENSATION APPLICATIONS • Idss SORTED IN 5mA PER BIN RANGE ELECTRICAL CHARACTERISTICS (Ta = 25°C) Caution! ESD sensitive device. SYMBOL PARAMETERS/TEST CONDITIONS 1 MIN TYP MAX UNITS P1dB Output Power at 1dB Compression VDS = 6V, IDS ≈ 50% IDSS, VG2S = 0V f = 12GHz 15.0 18.0 dBm G1dB Gain at 1dB Compression VDS = 6V, IDS ≈ 50% IDSS, VG2S = 0V f = 12GHz 17.5 19.5 dB NF Noise Figure VDS = 3V, IDS ≈ 15mA, VG2S = 0V f = 12GHz 1.2 dB Ga Associated Gain VDS = 3V, IDS ≈ 15mA, VG2S = 0V f = 12GHz 17.5 dB IDSS Saturated Drain Current VDS = 3V, VG1S = VG2S = 0 V 30 80 115 mA GM Transconductance VDS = 3V, VG1S = -0.5V, VG2S = 0 V 40 70 mS VP1 Pinch-off Voltage VDS = 3V, IDS = 1.0mA, VG2S = 0 V -1.5 -3.5 V VP2 Pinch-off Voltage VDS = 3V, IDS = 1.0mA, VG1S = 0 V -1.5 -3.5 V BVG2D Gate 2 to Drain Breakdown Voltage IG2D = 1.0mA, Gate 1 Open -10 -14 V BVG1S Gate 1 to Source Breakdown Voltage IG1S = 1.0mA, Gate 2 Open -6 -12 V RTH Thermal Resistance 125 oC/W |
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Similar Description - EPA030D |
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