ST7263BEx datasheet(117/186 Pages) STMICROELECTRONICS

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ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

117/186

11.5.7

I²C Control register (CR)

Reset value: 0000 0000 (00h)

ENGC

START

ACK

STOP

ITE

Read/write

[7:6] Reserved. Forced to 0 by hardware.

5 PE Peripheral enable.

This bit is set and cleared by software.

0: Peripheral disabled

1: Master/Slave capability

Note: When PE=0, all the bits of the CR register and the SR register except the

Stop bit are reset. All outputs are released while PE=0.

When PE=1, the corresponding I/O pins are selected by hardware as

alternate functions.

To enable the I²C interface, write the CR register TWICE with PE=1 as the

first write only activates the interface (only PE is set).

4 ENGC Enable General Call.

This bit is set and cleared by software. It is also cleared by hardware when the

interface is disabled (PE=0). The 00h General Call address is acknowledged (01h

ignored).

0: General Call disabled

1: General Call enabled

Note: In accordance with the I2C standard, when GCAL addressing is enabled, an

I2C slave can only receive data. It will not transmit data to the master.

3 START Generation of a Start condition. This bit is set and cleared by software. It is

also cleared by hardware when the interface is disabled (PE=0) or when the Start

condition is sent (with interrupt generation if ITE=1).

In master mode:

0: No start generation

1: Repeated start generation

In slave mode:

0: No start generation

1: Start generation when the bus is free

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