AD6657

Rev. 0 | Page 8 of 32

TIMING SPECIFICATIONS

otherwise noted.

Table 5.

Parameter

Description

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

SYNC to rising edge of CLK setup time

0.24

ns

SYNC to rising edge of CLK hold time

0.40

ns

SPI TIMING REQUIREMENTS

Setup time between the data and the rising edge of SCLK

2

ns

Hold time between the data and the rising edge of SCLK

2

ns

Period of the SCLK

40

ns

Setup time between CSB and SCLK

2

ns

Hold time between CSB and SCLK

2

ns

SCLK pulse width high

10

ns

SCLK pulse width low

10

ns

Time required for the SDIO pin to switch from an input to

an output relative to the SCLK falling edge

10

ns

Time required for the SDIO pin to switch from an output to

an input relative to the SCLK rising edge

10

ns

Timing Diagrams

N – 1

N + 1

N + 2

N + 3

N + 4

N + 5

N

CLK+

CLK–

DCO+

DCO–

D10+AB (MSB)

D10–AB (MSB)

D0+AB (LSB)

D0–AB (LSB)

VIN

1/

D10A

D10B

D10A

D10B

D10A

D10B

D10A

D10B

D10A

D10B

D10A

D10B

D0A

D0B

D10A

D10B

D0A

D0B

D0A

D0B

D0A

D0B

D0A

D0B

D0A

D0B

D0A

D0B

Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)

SYNC

CLK+

Figure 3. SYNC Input Timing Requirements