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PIC24F16KA102-I/SP Datasheet(PDF) 61 Page - Microchip Technology |
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PIC24F16KA102-I/SP Datasheet(HTML) 61 Page - Microchip Technology |
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61 / 254 page  © 2009 Microchip Technology Inc. Preliminary DS39927B-page 59 PIC24F16KA102 FAMILY TABLE 7-1: RESET FLAG BIT OPERATION 7.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. TABLE 7-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR IDLE (RCON<2>) PWRSAV #IDLE Instruction POR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — DPSLP (RCON<10>) PWRSAV #SLEEP instruction with DSCON <DSEN> set POR Note: All Reset flag bits may be set or cleared by the user software. REGISTER 7-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. Reset Type Clock Source Determinant POR FNOSC Configuration bits (FNOSC<10:8>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR |
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