TNETX3100PGC datasheet(72/80 Pages) TI1

72 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

operating characteristics over recommended operating conditions (see Figure 23)

EEPROM interface

NO.

PARAMETER

MIN

MAX

UNIT

fclock (ECLK)

Clock frequency, ECLK

kHz

td (ECLKH–EDIOL)

Delay time, from ECLK

↑ to EDIO↓ (see Note 14)

µs

td (EDIOL–ECLKL)

Delay time, from EDIO

↓ to ECLK↓ (see Note 14)

µs

td (ECLKL–EDIOX)

Delay time, from ECLK

↓ to EDIO changing (see Note 15)

µs

td (EDIOV–ECLKH)

Delay time, from EDIO valid output to ECLK

↑

µs

td (ECLKL–EDIOV)

Delay time, from ECLK

↓ to EDIO valid

µs

td (ECLKL–EDIOX)

Delay time, from ECLK

↓ to EDIO changing (see Note 16)

µs

td (ECLKH–EDIOX)

Delay time, from ECLK

↑ to EDIO invalid

µs

td (EDIOV–ECLKH)

Delay time, from EDIO valid input to ECLK

↑

µs

NOTES: 14. This is a start-condition delay time during ECLK high.

15. This is a changing-data condition delay time for output EDIO.

16. This is a changing-data condition delay time for input EDIO.

ECLK

(output)

EDIO

(output)

EDIO

(input)

VALID

Figure 23. EEPROM Interface Timing

TNETX3100PGC Datasheet(PDF) 72 Page - Texas Instruments

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