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SST49LF020 Datasheet(PDF) 19 Page - Silicon Storage Technology, Inc |
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SST49LF020 Datasheet(HTML) 19 Page - Silicon Storage Technology, Inc |
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19 / 38 page  Advance Information 2 Megabit LPC Flash SST49LF020 19 ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 526 FIGURE 11: SECTOR-ERASE TIMING DIAGRAM (LPC MODE) 526 ILL F23.3 RST# LFRAME# LAD[3:0] 0000b 011Xb 0101b 0101b 0101b 1010b X101b 1010b Tri-State TAR Load Address "5555" in 8 Clocks Write the 1st command to the device in LPC mode. Address 1 Clock 1 Clock 1st Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "AA" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb 1010b 1010b 1010b 0101b X010b 0101b Tri-State TAR Load Address "2AAA" in 8 Clocks Write the 2nd command to the device in LPC mode. Address 1 Clock 1 Clock 2nd Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "55" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb 0101b 0101b 0101b 1000b X101b 0000b Tri-State TAR Load Address "5555" in 8 Clocks Write the 3rd command to the device in LPC mode. Address 1 Clock 1 Clock 3rd Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "80" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb 0101b 0101b 0101b 1010b X101b 1010b Tri-State TAR Load Address "5555" in 8 Clocks Write the 4th command to the device in LPC mode. Address 1 Clock 1 Clock 4th Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "AA" in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb 1010b 1010b 1010b 0101b X010b 0101b XXXXb XXXXb XXXXb 0011b SAX 0000b Tri-State TAR Load Address "2AAA" in 8 Clocks Load Sector Address in 8 Clocks Write the 5th command to the device in LPC mode. Address 1 Clock 1 Clock 5th Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data "55" in 2 Clocks Load Data “30” in 2 Clocks 1111b 0000b LCLK RST# = VIH LFRAME# LAD[3:0] 0000b 011Xb Tri-State TAR Write the 6th command (target sector to be erased) to the device in LPC mode. SAX = Sector Address Address 1 Clock 1 Clock 6th Start Memory Write Cycle TAR Sync Data Internal erase start Internal erase start 1 Clock 2 Clocks 1111b 0000b CE# = VIL CE# = VIL CE# = VIL CE# = VIL CE# = VIL LCLK CE# xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb A[19:16] |
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